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RT3000A/b/c ? ds3000abc-00 may 2016 www.richtek.com 3 ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. 3-axis digital accelerometer general description the rt3000 is a low power and high accuracy 3 axis acceleration sensor with digital output for portable device. the part has user selectable full scales rages of 2g, 4g, 8g and 16g, and, it is capable of measuring accelerations with output data rates from 1hz to 200hz. the RT3000A is available in mqfn-16l 3x3, rt3000b in mqfn-12l 2x2 (col) and rt3000c in mdfn-10l 3x3 package. features ? ? ? ? ? user programmable 2g/ 4g/ 8g/ 16g full-scale ? ? ? ? ? i 2 c digital i/o interface ? ? ? ? ? user programmable operation modes : power down, normal mode and high resolution mode ? ? ? ? ? programmable interrupts for motion and orientation detections ? ? ? ? ? embedded fifo ? ? ? ? ? self-test function applications ? smartphones ? tablet pc ? notebook ? pnd ? gps ? remote controller ? gaming ? toys ordering information note : richtek products are : ? rohs compliant and compatible with the current require ments of ipc/jedec j-std-020. ? suitable for use in snpb or pb-free soldering processes. pin configurations (top view) mqfn -12l 2x2 (col) mqfn-16l 3x3 rt3000 package type qm : mqfn-16l 3x3 (m-type) qm : mqfn-12l 2x2 (col) (m-type) qm : mdfn-10l 3x3 (m-type) operating temperature range g : green (halogen free and pb free) a : mqfn-16l 3x3 b : mqfn-12l 2x2 (col) c : mdfn-10l 3x3 marking information 8e=ym dnn 8e= : product code ymdnn : date code RT3000Agqm 3p : product code w : date code 3pw rt3000bgqm 9f=ym dnn 9f= : product code ymdnn : date code rt3000cgqm mdfn-10l 3x3 vddio nc scl nc sda nc nc vdd nc gnd nc int1 res int2 nc nc 14 16 8 6 13 12 10 9 1 2 4 5 res 17 11 3 15 7 nc res vddio sda gnd gnd int1 int2 scl nc nc vdd 6 5 12 11 1 2 3 10 9 8 4 7 nc res int1 gnd vdd nc vddio nc scl sda 5 4 3 2 1 10 9 8 7 6 res 11
RT3000A/b/c 2 ds3000abc-00 may 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. function pin description RT3000A (mqfn-16l 3x3) name description 14 vdd power supply. 1 vddio power supply for i/o pins. 12 gnd ground. 6 sda i 2 c serial data. 4 scl i 2 c serial clock. 9 int1 interrupt 1. 11 int2 interrupt 2. 2, 5, 7, 8, 10, 13, 15, 16 nc no internal connection. (*note 1) 3 res reserved pin. (*note 2) 17 (exposed pad) res reserved pin. (*note 5) rt3000b mqfn-12l 2x2 (col) name description 7 vdd power supply. 3 vddio power supply for i/o pins. 8, 9 gnd ground. 2 sda i 2 c serial data. 12 scl i 2 c serial clock. 5 int1 interrupt 1. 6 int2 interrupt 2. 1, 4, 11 nc no internal connection. (*note 1) 10 res reserved pin (*note 3) rt3000c (mdfn-10l 3x3) name description 3 vdd power supply. 9 vddio power supply for i/o pins. 4 gnd ground. 7 sda i 2 c serial data. 6 scl i 2 c serial clock. 5 int1 interrupt 1. 1, 8, 10 nc no internal connection. (*note 1) 2 res reserved pin. (*note 4) 11 (exposed pad) res reserved pin. (*note 5) *note 1 : recommend floating or connect to vdd or gnd. *note 2 : must be floating or connect to vddio. *note 3 : must be floating or connect to gnd. *note 4 : must be floating or connect to vdd. *note 5 : must be floating.
RT3000A/b/c 3 ds3000abc-00 may 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. functional block diagram digital processing osc ad converter x,y,z sensor vdd cha gnd scl sda mtp ldo i/o control vddio int1 int2 operation power mode th e rt3000 has three different power modes: power down mode, normal mode and high resolution mode to offer the customer different power consumption and effective resolution options. the transitions between the power modes are illustrated in figure below when the rt3000 is in power-down mode, almost all internal blocks of the device are switched off except digital interfaces (i 2 c) are still active to allow communication with the device. the configuration registers content is preserved and output data registers keeping the last data sampled in memory before going into power-down mode. in normal mode or high resolution mode, it ? s depending on customer ? s application to set related register. self-test the rt3000 has the self-test feature for the sensor functionality check by applying electrostatic force to the sensor element. a static offset of the acceleration data could be observed when the self-test activate. the acceleration measurement range should be set to 2g before self-test is enabled. the self-test function is off when the self-test bit (sten) is programmed to ? 0 ? . when the self-test bit is programmed to ? 1 ? an actuation force is applied to the sensor, simulating a definite input acceleration. table 1 shows the typical offset differences of self-test for each axes. power down vdd power on nor. mode (normal power consumption and resolution) hr mode (highest power consumption and resolution) ctrl4_reg[3] = "1" ctrl4_reg[3] = "0" ctrl1_reg[7:4] = "0000" different mode switch time : 12/odr ms
RT3000A/b/c 4 ds3000abc-00 may 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. table 1. typical self-test offset difference values x-axis y-axis z-axis offset difference 80mg 80mg 80mg fifo the rt3000 included an integrated 32 frame fifo for each axis. the fifo which can be configured to operate in following mode fifo mode in fifo mode the acceleration data of selected axis are stored in the buffer until full. when the buffer is full, the data collection is stopped. once the buffer is full; a fifo- full interrupt is generated if it has been enabled. stream mode in stream mode the acceleration data of selected axis are stored in the buffer until full. when the buffer is full, the data continues and oldest entry is discarded. bypass mode in bypass mode, only the current sensor data can be read out from the fifo. the fifo behaves like the stream mode with a depth of one, compared to reading the data from normal data register. trigger mode in trigger mode is a combination of the stream and fifo modes described above. in this mode, the fifo buffer starts operating in stream mode and switches to fifo mode when the selected interrupt occurs. start up and read data sequence after vdd power up 32ms power down mode set odr rate : ctrl1_reg[7:4] set operation mode : ctrl4_reg[3] read sts_reg zyxda = '1' read xdata_l/xdata_h read ydata_l/ydata_h read zdata_l/zdata_h data processing no
RT3000A/b/c 5 ds3000abc-00 may 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. recommended operating conditions (note 3) ? input voltage range ----------------------------------------------------------------------------------------- 2v to 3.6v ? ambient temperature range ------------------------------------------------------------------------------- ? 40 c to 85 c mechanical characteristics parameter symbol conditions min typ max unit acceleration range fs 2g customer programmable via serial digital interface -- ? 2 -- g fs 4g -- ? 4 -- g fs 8g -- ? 8 -- g fs 16g -- ? 16 -- g sensitivity s 2g fs 2g -- 16384 -- lsb/g s 4g fs 4g -- 8192 -- lsb/g s 8g fs 8g -- 4096 -- lsb/g s 16g fs 16g -- 2048 -- lsb/g zero-g offset offset 2g fs 2g -- ? 45 -- mg zero-g offset temperature shift tco 2g fs 2g , ? 40c ? t a ? 85c -- ? 1 -- mg/ ? c sensitivity temperature shift tcs 2g fs 2g , ? 40c ? t a ? 85c -- ? 0.05 -- %/ ? c nonlinearity nl max. deviation to best fit straight line -- ? 0.5 -- %fs noise n rms fs 2g -- 3 -- mg cross axis sensitivity cas relative contribution from the other to axes -- ? 1.25 -- % (v dd = 2.5v, t a = 25 c unless otherwise specified) absolute maximum ratings (note 1) ? vdd supply voltage ----------------------------------------------------------------------------------------- ? 0.2v to 4v ? vddio supply voltage -------------------------------------------------------------------------------------- ? 0.2v to 4v ? scl, sda, int1, int2 -------------------------------------------------------------------------------------- ? 0.2v to (vddio + 0.3v) ? storage temperature range ------------------------------------------------------------------------------- ? 40 c to 125 c ? esd susceptibility (note 2) hbm (human body model) --------------------------------------------------------------------------------- 2kv cdm (charged device model) ----------------------------------------------------------------------------- 1kv ? mechanical shock (unpowered) ---------------------------------------------------------- ---------------- 10000g for 0.2ms electrical characteristics (v dd = 2.5v, t a = 25 c unless otherwise specified) parameter symbol conditions min typ max unit supply voltage - core v dd 2 2.5 3.6 v supply voltage ? i/o v ddio 1.5 2.5 3.6 v input voltage low v il i 2 c -- -- 0.3 v ddio v input voltage high v ih i 2 c 0.7 v ddio -- -- v
RT3000A/b/c 6 ds3000abc-00 may 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. electrical characteristics : i 2 c interface parameter symbol standard mode fast mode unit min max min max scl clock frequency f sclk 10 100 10 400 khz hold time after (repeated) start condition. after this period, the first clock is generated t hdsta 4 -- 0.6 -- ? s low period of the scl clock t low 4.7 -- 1.3 -- ? s high period of the scl clock t high 4.0 -- 0.6 -- ? s set-up time for a repeated start condition t susta 4.7 -- 0.6 -- ? s data hold time t hddat -- 120 -- 120 ns t sudat data set-up time t sudat 250 -- 100 ns rise time of both sda and scl signals t r -- 1000 -- 300 ns fall time of both sda and scl signals t f -- 300 -- 300 ns set-up time for stop condition t susto 4.0 -- 0.6 -- ? s bus free time between a stop and start condition 4.7 -- 1.3 -- ? s parameter symbol conditions min typ max unit output voltage low v ol -- -- 0.2 v ddio v output voltage high v oh 0.8 v ddio -- -- v current consumption @ normal mode i ddn odr = 200hz -- 120 -- ? a current consumption @ normal mode i ddn odr = 25hz -- 15 -- ? a current consumption @ power down mode i dds -- 1 -- ? a wake-up time t wu time from power down mode to normal mode or high resolution mode -- 1.8 -- ms start-up time t su time for power on reset. -- 40 -- ms note 1. stresses beyond those listed ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions may affect device reliability. note 2. devices are esd sensitive. handling precaution is recommended. note 3. the device is not guaranteed to function outside its operating conditions.
RT3000A/b/c 7 ds3000abc-00 may 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. figure 1. timing chart of the i2c figure 2. write command figure 3. read data v ih v il t f t low t hdsta t sclk t hddat t sudat t high t susta t hdsta t susto t buf t r start start stop sda scl wr ack device address register address write data ack ack start stop sda scl wr ack device address register address start stop sda scl rd ack device address read data start stop ack nak
RT3000A/b/c 8 ds3000abc-00 may 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. typical application circuit rt3000b (mqfn-12l 2x2) rt3000c (mdfn-10l 3x3) RT3000A (mqfn-16l 3x3) 1 2 3 4 10 9 8 7 12 11 5 6 sda 10k scl v ddio 0.1f int1 int2 v dd 10k 0.1f 1 2 3 4 5 10 9 8 7 6 11 0.1f v dd int1 v ddio sda scl 10k 10k 0.1f v ddio scl sda int2 int1 v dd 0.1f 0.1f 10k 10k 17 1 2 3 4 5 13 12 11 10 9 16 15 14 6 7 8
RT3000A/b/c 9 ds3000abc-00 may 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. register map register address type name default value bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0x06 r/w ctrl_reg0 0000 0000 0 0 li r_click -- 0 inaen clicken aoien 0x0f r who_am_i 0011 0011 0 0 1 1 0 0 1 1 0x20 r/w ctrl_reg1 0000 0111 odr3 odr2 oddr1 odr0 0 zen yen xen 0x21 r/w ctrl_reg2 0000 0000 -- -- hp cf2 hpcf1 fdout hpclick -- hpis1 0x22 r/w ctrl_reg3 0000 0000 i1_click i1_aoi i1_inact i1_drdy1 -- i1_wtm i1_orun -- 0x23 r/w ctrl_reg4 0000 0000 bdu bigen fs1 fs0 hr -- sten -- 0x24 r/w ctrl_reg5 0000 0000 boot fi foen 0 0 lir_aoi ods_aoi -- -- 0x25 r/w ctrl_reg6 0000 0000 i2_click_en i2_aoi -- i2_boot -- -- hl_active -- 0x27 r sts_reg -- zyxover zover yover xover zyxda zda yda xda 0x28 r out_x_l output xd7 xd6 xd5 xd4 xd3 xd2 xd1 xd0 0x29 r out_x_h output xd15 xd14 xd13 xd12 xd11 xd10 xd9 xd8 0x2a r out_y_l output yd7 yd6 yd5 yd4 yd3 yd2 yd1 yd0 0x2b r out_y_h output yd15 yd14 yd13 yd12 yd11 yd10 yd9 yd8 0x2c r out_z_l output zd7 zd6 zd5 zd4 zd3 zd2 zd1 zd0 0x2d r out_z_h output zd15 zd 14 zd13 zd12 zd11 zd10 zd9 zd8 0x2e r/w fifo_cfg 0000 0000 fm1 fm0 tr fth4 fth3 fth2 fth1 fth0 0x2f r fifo_src -- wtm ovrn_ fifo empty fss4 fss3 fss2 fss1 fss0 0x30 r/w aoi_cfg 0000 0000 aoi1 aoi0 zhie/ zupe1 zlie/ zdowne1 yhie/ yupe1 ylie/ ydowne1 xhie/ xupe1 xlie/ xdowne1 0x31 r aoi_src -- -- ia1 zh1 zl1 yh1 yl1 xh1 xl1 0x32 r/w aoi_ths 0000 0000 -- aoih6 ao ih5 aoih4 aoih3 ao ih2 aoih1 aoih0 0x33 r/w aoi_dur 0000 0000 -- aoid6 aoid5 aoid4 aoid3 aoid2 aoid1 aoid0 0x38 r/w click_cfg 0000 0000 -- -- zd en zsen yden ysen xden xsen 0x39 r click_src -- -- ia dclick sclick click_sign zclick yclick xclick 0x3a r/w click_ths 0000 0000 -- cths6 ct hs5 cths4 cths3 cths2 cths1 cths0 0x3b r/w time_limit 0000 0000 -- tli6 tli5 tli4 tli3 tli2 tli1 tli0 0x3c r/w time_latency 0000 0000 tla7 tla6 tla5 tla4 tla3 tla2 tla1 tla0 0x3d r/w time_window 0000 0000 tw7 tw6 tw5 tw4 tw3 tw2 tw1 tw0 0x3e r/w inact_ths 0000 0000 inact_sts inah6 in ah5 inah4 inah3 in ah2 inah1 inah0 0x3f r/w inact_dur 0000 0000 inad7 inad6 inad 5 inad4 inad3 in ad2 inad1 inad0 ?
RT3000A/b/c 10 ds3000abc-00 may 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. register 0x06 (ctrl_reg0) bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 lir_click 0 0 inaen clicken aoien bit type name default description 5 r/w lir_click 0 latch click event interrupt. 0 : disable; 1 : enable 2 r/w inaen 0 inactivity detec tion. 0 : disable; 1 : enable 1 r/w clicken 0 click detection. 0 : disable; 1 : enable 0 r/w aoien 0 aoien detection. 0 : disable; 1 : enable register 0x0f (who_am_i) bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 1 1 0 0 1 1 bit type name default description [7:0] r id7:id0 00110011 device id register 0x20 (ctrl_reg1) bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 odr3 odr2 odr1 odr0 0 zen yen xen bit type name default description [7:4] r/w odr3:odr0 0000 data rate selection. 0000 : power down mode 0001 : 1hz 0010 : 10hz 0011 : 25hz 0100 : 50hz 0101 : 100hz 0110 : 200hz 2 r/w zen 1 z axis enable. 0 : disable; 1 : enable 1 r/w yen 1 y axis enable. 0 : disable; 1 : enable 0 r/w xen 1 x axis enable. 0 : disable; 1 : enable register table lists (i2c slave address : 19h)
RT3000A/b/c 11 ds3000abc-00 may 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. register 0x21 (ctrl_reg2) bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 hpcf2 hpcf1 fdout hpclick 0 hpis1 bit type name default description [5:4] r/w hpcf2 : hpcf1 00 high pass filter cut off frequency selection. 00 : odr/12.5 01 : odr/25 10 : odr/50 11 : odr/75 3 r/w fdout 0 filtered data selection. 0: high pass filter bypassed; 1: data fr om high pass filter sent to output register and fifo 2 rw hpclick 0 high pass filter enabled for click function. 0 : disable; 1 : enable 0 r/w hpis1 0 high pass filter enabled fo r aoi function. 0: disable; 1 : enable register 0x22 (ctrl_reg3) bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 i1_click i1_aoi i1_inact i 1_drdy1 0 i1_wtm i1_orun 0 bit type name default description 7 r/w i1_click 0 click interrup t on int1. 0 : disable; 1 : enable 6 r/w i1_aoi 0 aoi interrupt on int1. 0 : disable; 1 : enable 5 r/w i1_inact 0 inactivity interrupt on int1. 0 : disable; 1 : enable 4 r/w i1_drdy1 0 data-ready interrupt on int1. 0 : disable; 1 : enable 2 r/w i1_wtm 0 fifo watermark interr upt on int1. 0 : disable; 1 : enable 1 r/w i1_orun 0 fifo overrun interrup t on int1. 0 : disable; 1 : enable register 0x23 (ctrl_reg4) bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 bdu bigen fs1 fs0 hr 0 sten 0 bit type name default description 7 r/w bdu 0 block data update. 0: disable; 1: enable 6 r/w bigen 0 big endian enable. 0: data lsb @ lower address. 1 : data msb @ lower address [5:4] r fs1:fs0 00 full scale range selection. 00 : ? 2g; 01 : ? 4g; 10 : ? 8g; 11 : ? 16g 3 r/w hr 0 high resolution mode. 0 : disable; 1 : enable 1 r/w sten 0 self-test mode. 0 : disable; 1 : enable
RT3000A/b/c 12 ds3000abc-00 may 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. register 0x24 (ctrl_reg5) bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 boot fifoen 0 0 lir_aoi ods_aoi 0 0 bit type name default description 7 r/w boot 0 reboot. 0: disable; 1 : enable 6 r/w fifoen 0 fifo enable. 0 : disable; 1 : enable 3 r/w lir_aoi 0 latch aoi event interrupt. 0 : disable; 1 : enable 2 r/w ods_aoi 0 orientation detection selecti on. 0: 6d orientation; 1: 4d orientation register 0x25 (ctrl_reg6) bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 i2_click_en i2_aoi 0 i2_boot 0 0 hl_active 0 bit type name default description 7 r/w i2_click_en 0 click interrupt on int2 pin. 0 : disable; 1 : enable 6 r/w i2_aoi 0 aoi interrupt on int2 pin. 0 : disable; 1 : enable 4 r/w i2_boot 0 boot status on int2 pin. 0 : disable; 1 : enable 1 r/w hl_active 0 active high/low level for inte rrupt pins. 0: active high; 1: active low register 0x27 (sts_reg) bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 zyxover zover yover xo ver zyxda zda yda xda bit type name default description 7 r zyxover 0 x, y and z axis data overrun. 0 : normal; 1: overrun 6 r zover 0 z axis data overrun. 0: normal; 1 : overrun 5 r yover 0 y axis data overrun. 0: normal; 1 : overrun 4 r xover 0 x axis data overrun. 0: normal; 1 : overrun 3 r zyxda 0 x, y and z axis new data ava ilable. 0 : not available; 1 : available 2 r zda 0 z axis new data available. 0 : not available; 1 : available 1 r yda 0 y axis new data available. 0 : not available; 1 : available 0 r xda 0 x axis new data available. 0 : not available; 1 : available
RT3000A/b/c 13 ds3000abc-00 may 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. register 0x28 (out_x_l) bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 xd7 xd6 xd5 xd4 xd3 xd2 xd1 xd0 bit type name default description [7:0] r xd7:xd0 00000000 low byte of x axis data. register 0x29 (out_x_h) bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 xd15 xd14 xd13 xd12 xd11 xd10 xd9 xd8 bit type name default description [7:0] r xd15:xd8 00000000 high byte of x axis data. register 0x2a (out_y_l) bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 yd7 yd6 yd5 yd4 yd3 yd2 yd1 yd0 bit type name default description [7:0] r yd7:yd0 00000000 low byte of y axis data. register 0x2b (out_y_h) bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 yd15 yd14 yd13 yd12 yd11 yd10 yd9 yd8 bit type name default description [7:0] r yd15:yd8 00000000 high byte of y axis data. register 0x2c (out_z_l) bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 zd7 zd6 zd5 zd4 zd3 zd2 zd1 zd0 bit type name default description [7:0] r zd7:zd0 0 low byte of z axis data. register 0x2d (out_z_h) bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 zd15 zd14 zd13 zd12 zd11 zd10 zd9 zd8 bit type name default description [7:0] r zd15:zd8 0 high byte of z axis data.
RT3000A/b/c 14 ds3000abc-00 may 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. register 0x2e (fifo_cfg) bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 fm1 fm0 tr fth4 fth3 fth2 fth1 fth0 bit type name default description [7:6] r/w fm1:fm0 00 fifo mode selection. 00 : bypass mode 01 : fifo mode 10 : stream mode 11 : trigger mode 5 r/w tr 0 trigger selection. 0 : trigger event liked to trigger signal on aoi 1 : trigger event liked to trigger signal on click [4:0] r/w fth4:fth0 00000 fth[4:0] bits are intended to define the watermark level. when fifo content exceeds this value, the wtm flag is set to ?1? in the fifo_src register. register 0x2f (fifo_src) bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 wtm ovrn_fifo empty fss4 fss3 fss2 fss1 fss0 bit type name default description 7 r wtm 0 wtm flag is set high when fifo content exceeds watermark level. 6 r ovrn_fifo 0 ovrn flag is set high when fifo buffer is full, this means that the fifo buffer contains 32 unread samples. 5 r empty 0 empty flag is set high when all fifo samples have been read and fifo is empty. [4:0] r fss4:fss0 00000 fss[4:0] field always contains the current number of unread samples stored in the fifo buffer.
RT3000A/b/c 15 ds3000abc-00 may 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. register 0x30 (aoi_cfg) bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 aoi1 aoi0 zhie/ zupe1 zlie / zdowne1 yhie / yupe1 ylie / ydowne1 xhie / xupe1 xlie / xdowne1 bit type name default description [7:6] r/w aoi1:aoi0 00 motion detection mode selection. 00 : wakeup 01 : 6d/4d movement 10 : free-fall 11 : 6d/4d position 5 r/w zhie/zupe1 0 z-axis high-g interrupt gener ation for aoi function. 0: disable; 1: enable 4 r/w zlie/zdowne1 0 z-axis low-g interrupt gener ation for aoi function. 0: disable; 1: enable 3 r/w yhie/yupe1 0 y-axis high-g interrupt gen eration for aoi function. 0: disable; 1: enable 2 r/w ylie/ydowne1 0 y-axis low-g interrupt generation for aoi function. 0: disable; 1: enable 1 r/w xhie/xupe1 0 x-axis high-g interrupt gen eration for aoi function. 0: disable; 1: enable 0 r/w xlie/xdowne1 0 x-axis low-g interrupt generation for aoi function. 0: disable; 1: enable register 0x31 (aoi_src) bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 ia1 zh1 zl1 yh1 yl1 xh1 xl1 bit type name default description 6 r ia1 0 aoi status. 0: no event; 1: one or more events have been generated 5 r zh1 0 z-axis high-g event status for aoi function. 0: inactive; 1: active 4 r zl1 0 z-axis low-g event status for aoi function. 0: inactive; 1: active 3 r yh1 0 y-axis high-g event status fo r aoi function. 0: inactive; 1: active 2 r yl1 0 y-axis low-g event status for aoi function. 0: inactive; 1: active 1 r xh1 0 x-axis high-g event status fo r aoi function. 0: inactive; 1: active 0 r xl1 0 x-axis low-g event status for aoi function. 0: inactive; 1: active
RT3000A/b/c 16 ds3000abc-00 may 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. register 0x32 (aoi_ths) bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 aoih6 aoih5 aoih 4 ao ih3 aoih2 ao ih1 aoih0 bit type name default description [6:0] r/w aoih6:aoih0 0000000 aoi threshold. register 0x33 (aoi_dur) bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 aoid6 aoid5 aoid4 ao id3 aoid2 ao id1 aoid0 bit type name default description [6:0] r/w aoid6:aoid0 0000000 aoi duration. unit: 1/odr register 0x38 (click_cfg) bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 zden zsen yden ysen xden xsen bit type name default description 5 r/w zden 0 double click detection on z-axis. 0 : disable; 1 : enable 4 r/w zsen 0 single click detection on z-axis. 0 : disable; 1 : enable 3 r/w yden 0 double click detection on y-axis. 0 : disable; 1 : enable 2 r/w ysen 0 single click detection on y-axis. 0 : disable; 1 : enable 1 r/w xden 0 double click detection on x-axis. 0 : disable; 1 : enable 0 r/w xsen 0 single click detection on x-axis. 0 : disable; 1 : enable
RT3000A/b/c 17 ds3000abc-00 may 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. register 0x39 (click_src) bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 ia dclick sclick click_si gn zclick yclick xclick bit type name default description 6 r ia 0 click interrupt status. 0 : inactive; 1 : active 5 r dclick 0 double-click interrupt status. 0 : inactive; 1 : active 4 r sclick 0 single-click interrupt status. 0 : inactive; 1 : active 3 r click_sign 0 sign of click event status . 0 : positive; 1 : negative 2 r zclick 0 click event detection status on z- axis. 0 : not detected; 1 : detected 1 r yclick 0 click event detection status on y- axis. 0 : not detected; 1 : detected 0 r xclick 0 click event detection status on x- axis. 0 : not detected; 1 : detected register 0x3a (click_ths) bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 cths6 cths5 cths4 cths3 cths2 cths1 cths0 bit type name default description [6:0] r/w cths6: cths0 0000000 click threshold. register 0x3b (time_limit) bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 tli6 tli5 tli4 tl i3 tli2 tli1 tli0 bit type name default description [6:0] r/w tli6: tli0 0000000 c lick time limit. unit : 1/odr register 0x3c (time_latency) bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 tla7 tla6 tla5 tla4 tla3 tla2 tla1 tla0 bit type name default description [7:0] r/w tla7: tla0 00000000 clic k time latency. unit : 1/odr register 0x3d (time_window) bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 tw7 tw6 tw5 tw4 tw3 tw2 tw1 tw0 bit type name default description [7:0] r/w tw7: tw0 00000000 click time window. unit: 1/odr
RT3000A/b/c 18 ds3000abc-00 may 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. register 0x3e (inact_ths) bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 inact_sts inah6 in ah5 inah4 inah3 in ah2 inah1 inah0 bit type name default description 7 r inact_sts 0 inactivity interrupt status. 0 : inactive; 1 : active [6:0] r/w inah6 : inah0 000000 0 inactivity threshold. register 0x3f (inact_dur) bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 inad7 inad6 inad 5 inad4 inad3 inad2 inad1 inad0 bit type name default description [7:0] r/w inad7 : inad0 00000000 i nactivity duration. unit: 16/odr sensing axes orientation the sensor is at rest in gravity filed according to following figure, and the output signals are : ? 0g for the x-axis ? 0g for the y-axis ? +1g for the z-axis mdfn-10l 3x3 mqfn-16l 3x3 gravity y z x gravity x z y gravity y z x mq fn-12l 2x2 (col)
RT3000A/b/c 19 ds3000abc-00 may 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. soldering guidelines condition contents preheat temperature 175 ( ? 25) ? c 60 to 180 seconds temperature maintained above 217 ? c 60 to 150 seconds time within 5 ? c of actual peak temperature 20 to 40 seconds peak temperature 260 ? c ramp-down rate 6 ? c /second max. time 25 ? c to peak temperature 8 minutes max. ? layout considerations ? no extra traces and components under the device. ? do not place any components or vias at a distance less than 2 mm from the device. ? the solder mask opening must be larger than the land pad. ? use a pick and place machine and the solder paste thickness must be as uniform as possible to avoid uneven stress.
RT3000A/b/c 20 ds3000abc-00 may 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. recommended land pattern rt3000b (mqfn-12l 2x2) rt3000c (mdfn-10l 3x3) 1 1 RT3000A (mqfn-16l 3x3) 1
RT3000A/b/c 21 ds3000abc-00 may 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. outline dimension m-type 16l qfn 3x3 package symbol dimensions in millimeters dimensions in inches min. max. min. max. a 0.900 1.000 0.035 0.039 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.200 0.300 0.008 0.012 d 2.900 3.100 0.114 0.122 d2 1.250 1.350 0.049 0.053 e 2.900 3.100 0.114 0.122 e2 1.250 1.350 0.049 0.053 e 0.500 0.020 l 0.300 0.400 0.012 0.016 l1 0.400 0.500 0.016 0.020 k 0.050 0.150 0.002 0.006 ?
? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. RT3000A/b/c 22 ds3000abc-00 may 2016 www.richtek.com m-type 12l qfn 2x2 (col) package symbol dimensions in millimeters dimensions in inches min. max. min. max. a 0.900 1.000 0.035 0.039 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.200 0.300 0.008 0.012 d 1.900 2.100 0.075 0.083 e 1.900 2.100 0.075 0.083 e 0.500 0.020 l 0.250 0.350 0.010 0.014 l1 0.325 0.425 0.013 0.017 k 0.025 0.125 0.001 0.005 ?
RT3000A/b/c 23 ds3000abc-00 may 2016 www.richtek.com richtek technology corporation 14f, no. 8, tai yuen 1 st street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 richtek products are sold by description only. richtek reserves the right to change the circuitry and/or specifications without notice at any time. customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a richtek product. information furnish ed by richtek is believed to be accurate and reliable. however, no responsibility is assumed by richtek or its subsidiaries for its use; nor for any infringeme nts of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of r ichtek or its subsidiaries. m-type 10l dfn 3x3 package min. max. min. max. a 0.900 1.000 0.035 0.039 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.200 0.300 0.008 0.012 d 2.950 3.050 0.116 0.120 d2 2.150 2.250 0.085 0.089 e 2.950 3.050 0.116 0.120 e2 0.950 1.050 0.037 0.041 e l 0.300 0.400 0.012 0.016 l1 0.400 0.500 0.016 0.020 k 0.050 0.150 0.002 0.006 symbol dimensions in millimeters dimensions in inches 0.500 0.020

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